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ks8695x integrated multi-port high-performance gateway solution rev. 1.03 xcelerouter is a trademark of micrel, inc. amd is a registered trademark of advanced mi cro devices, inc. arm is a trademark o f advanced risc machines ltd. intel is a registered trademark of intel corporation. wi nce is a registered trademark of microsoft corporation. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 ( 408 ) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com june 2006 m9999-060106 general description the centaur ks8695x, multi-port gateway-on-a-chip, delivers a new level of networking integration and performance for accelerating broadband gateway development. key components integrated in the ks8695x include: ? integrated layer 2 managed switch with five fast ethernet transceivers and patented mixed-signal low- power technology, five media access control (mac) units, a high-speed non-blocking switch fabric, a dedicated address look-up engine, an on-chip frame buffer memory, and led controls. one port is partitioned for wan interface with the other four ports for lan access. ? a 166mhz arm? (arm992t) processor with memory management unit (mmu) and 8kb i-cache and 8kb d- cache. ? xcelerouter? technology for the wan and lan interfaces. ? shared programmable 8/16/32-bit data bus and 22-bit address bus with up to 64mb total memory space for sdram, rom, flash, sram, and all peripheral devices. ? other peripheral support logic including gpio, a watchdog timer, an interrupt controller, and a jtag debugging interface. complete hardware and software reference designs are available. the ks8695x represents a new level of total solution optimized for broadband gateway system development and renders speedy routing performance and connectivity interfaces for value-added networking expansions. functional diagram
micrel, inc. ks8695x june 2006 2 m9999-060106 features ? the centaur ks8695x featuring xcelerouter tech- nology is a single-chip multi-port gateway-on-a-chip with all the key components integrated for a high-perfor- mance and low-cost broadband gateway. ? arm922t high-performance cpu core ? arm922t core at 166mhz ? 8kb i-cache and 8kb d-cache ? memory management unit (mmu) for linux and wince ? ? 32-bit arm and 16-bit thumb instruction sets for smaller memory footprints ? xcelerouter technology ? tcp/udp/ip packet header checksum generation to offload cpu tasks ? ipv4 packet filtering on checksum errors ? automatic error packet discard ? integrated ethernet transceivers and switch engine ? five 10/100 transceivers and five macs (1p for wan interface, 4p for lan switching) ? 10base-t, 100base-tx, and 100base-fx modes (fx on the wan port) ? on-chip sram as frame buffer memory ? wire-speed switching ? vlan id and 802.1p tag/untag options ? extensive mib counter management support ? igmp snooping for multicast packet filtering ? port-based vlan ? qos/cos packet prioritization support: per port, 802.1p and diffserv-based ? 802.1d spanning tree protocol support ? dedicated 1k entry look-up engine ? automatic mdi/mdi-x crossover on all ports ? port mirroring/monitoring/sniffing ? broadcast storm protection with % control ? full- and half-duplex ow control ? memory and external i/o interfaces ? 8/16/32-bit wide shared data path for sdram, rom/sram/flash and external i/o ? total memory space up to 64mb ? intel ? /amd ? -type flash support ? wan and lan dma engines and fifo ? dma engine with burst mode support for efficient wan and lan data transfers ? fifos for back-to-back packet transfers ? peripheral support ? 8/16/32-bit external i/o interface supporting pcmcia or generic cpu/dsp host i/f ? eight general-purpose input/output (gpio) ? two 32-bit timer counters (one watchdog) ? interrupt controller ? arm922t jtag debug interface ? power management ? reduced cpu and system clock speeds ? system design ? up to 166mhz cpu and 125mhz bus speed ? reference hw/sw evaluation kit ? hardware evaluation board (passes class b emi) ? board support package including firmware source codes, linux kernel, and software stacks ? documentation for design and programming ? commercial temperature range: 0c to +70c ? available in 208-pin pqfp applications ? multi-port broadband gateway ? multi-port firewall and vpn appliances ? combination wireless and wireline gateway ? multi-port voip gateway ? fiber-to-the-home managed cpe ordering information part number standard pb (lead)-free temperature range package ks8695x KSZ8695X 0 to +70c 208-pin pqfp
micrel, inc. ks8695x june 2006 3 m9999-060106 revision history revision date summary of changes 1.00 05/24/04 created. 1.01 06/17/04 updated system clock. 1.02 10/26/04 updated timing diagrams: sram read and writ e, sdram read and write, and external i/o read/write cycles. 1.03 06/01/06 adde d pb-free option.
micrel, inc. ks8695x june 2006 4 m9999-060106 contents system level applications...................................................................................................... ............................................. 5 pin descr iption ................................................................................................................ ...................................................... 6 pin confi guration .............................................................................................................. .................................................. 13 functional d escripti on ......................................................................................................... .............................................. 14 introduction ................................................................................................................... .................................................... 14 cpu features ................................................................................................................... ................................................ 14 advanced memory cont roller features ............................................................................................ ................................ 14 direct memory access (dma) engines ............................................................................................. ............................... 14 xcelerouter technol ogy ......................................................................................................... ......................................... 15 switch engine .................................................................................................................. ................................................. 15 network in terface.............................................................................................................. ................................................ 15 peripherals.................................................................................................................... .................................................... 15 other fe atures................................................................................................................. ................................................. 15 signal descr iption............................................................................................................. .................................................. 16 system level hardware interfaces............................................................................................... .................................... 16 configurat ion pins............................................................................................................. ................................................ 16 reset.......................................................................................................................... ....................................................... 17 system clock ................................................................................................................... ................................................. 17 signal descripti ons by group ................................................................................................... ........................................ 18 address map and regi ster description........................................................................................... ................................. 26 memory map ..................................................................................................................... ................................................ 26 memory map example............................................................................................................. ......................................... 26 register description........................................................................................................... ............................................... 26 system registers............................................................................................................... ............................................... 26 memory controller in terface registers .......................................................................................... ................................... 26 wan dma r egisters .............................................................................................................. .......................................... 27 lan dma re gisters.............................................................................................................. ............................................ 28 uart regi sters ................................................................................................................. ............................................... 29 interrupt contro ller registers................................................................................................. ........................................... 29 timer regi sters................................................................................................................ ................................................. 29 general purpose i/o registers.................................................................................................. ....................................... 29 switch engine config uration registers .......................................................................................... .................................. 30 miscellaneous registers ........................................................................................................ ........................................... 30 absolute maxi mum ratings ....................................................................................................... ........................................ 31 operating ratings .............................................................................................................. ................................................. 31 electrical char acteristics ..................................................................................................... .............................................. 31 ldo options .................................................................................................................... .................................................... 33 timing di agrams ................................................................................................................ ................................................. 34 package info rmation............................................................................................................ ............................................... 39
micrel, inc. ks8695x june 2006 5 m9999-060106 system level applications tm tm figure 1. ks8695x applications
micrel, inc. ks8695x june 2006 6 m9999-060106 pin description pin number pin name type (1) pin function 1 vdd-io p 3.3v digital i/o circuitry v dd . 2 vss-io gnd digital i/o v ss . 3 addr10 o address bit. 4 addr9 o address bit. 5 addr8 o address bit. 6 addr7 o address bit. 7 addr6 o address bit. 8 addr5 o address bit. 9 addr4 o address bit. 10 addr3 o address bit. 11 vdd-io p 3.3v digital i/o circuitry v dd . 12 vss-io gnd digital i/o v ss . 13 addr2 o address bit. 14 addr1 o address bit. 15 addr0 o address bit. 16 sdcsn1 o sdram chip select. active low chip select pins for sdram. 17 sdcsn0 o sdram chip select. active low chip select pins for sdram. 18 sdrasn o sdram row address strobe. active low. 19 sdcasn o sdram column a ddress strobe. active low. 20 sdwen o sdram write enable. active low. 21 vdd-io p 3.3v digital i/o circuitry v dd . 22 vss-io gnd digital i/o v ss . 23 sdoclk o system/sdram clock out. 24 sdiclk i sdram clock in. 25 vdd-core p 1.8v digital core v dd . 26 vss-core gnd digital core v ss . 27 sdqm3 o sdram data input/output mask. 28 sdqm2 o sdram data input/output mask. 29 sdqm1 o sdram data input/output mask. 30 sdqm0 o sdram data input/output mask. 31 data31 i/o external data bit. 32 data30 i/o external data bit. note : 1. gnd = ground. p = power supply. i = input. o = output. i/o = bidirectional.
micrel, inc. ks8695x june 2006 7 m9999-060106 pin number pin name type (1) pin function 33 data29 i/o external data bit. 34 vdd-io p 3.3v digital i/o circuitry v dd . 35 vss-io gnd digital i/o v ss . 36 data28 i/o external data bit. 37 data27 i/o external data bit. 38 data26 i/o external data bit. 39 data25 i/o external data bit. 40 data24 i/o external data bit. 41 data23 i/o external data bit. 42 data22 i/o external data bit. 43 vdd-core p 1.8v digital core v dd . 44 vss-core gnd digital core v ss . 45 data21 i/o external data bit. 46 data20 i/o external data bit. 47 vdd-io p 3.3v digital i/o circuitry v dd . 48 vss-io gnd digital i/o v ss . 49 data19 i/o external data bit. 50 data18 i/o external data bit. 51 data17 i/o external data bit. 52 data16 i/o external data bit. 53 vdd-io p 3.3v digital i/o circuitry v dd . 54 vss-io gnd digital i/o v ss . 55 data15 i/o external data bit. 56 data14 i/o external data bit. 57 data13 i/o external data bit. 58 data12 i/o external data bit. 59 data11 i/o external data bit. 60 data10 i/o external data bit. 61 data9 i/o external data bit. 62 data8 i/o external data bit. 63 vdd-io p 3.3v digital i/o circuitry v dd . 64 vss-io gnd digital i/o v ss . 65 data7 i/o external data bit. note : 1. gnd = ground. p = power supply. i/o = bidirectional.
micrel, inc. ks8695x june 2006 8 m9999-060106 pin number pin name type (1) pin function 66 data6 i/o external data bit. 67 data5 i/o external data bit. 68 data4 i/o external data bit. 69 data3 i/o external data bit. 70 data2 i/o external data bit. 71 data1 i/o external data bit. 72 data0 i/o external data bit. 73 vdd-io p 3.3v digital i/o circuitry v dd . 74 vss-io gnd digital i/o v ss . 75 ecsn2 o external i/o device chip select. active low. 76 ecsn1 o external i/o device chip select. active low. 77 ecsn0 o external i/o device chip select. active low. 78 ewaitn i external wait. active low. 79 vdd-io p 3.3v digital i/o circuitry v dd . 80 vss-io gnd digital i/o v ss . 81 rcsn1 o rom/sram/flash chip select. active low. 82 rcsn0 o rom/sram/flash chip select. active low. 83 wrsto o watchdog timer reset output. 84 test3 nc this pin must be left as no connect. 85 eroen/ wrstpls o/i rom/sram/flash and external i/o output enable. active low. /wrsto polarity select. 86 erwen3/ tictestenn o external i/o and rom/sram/flash write byte enable. active low. 87 erwen2/ testreqa o external i/o and rom/sram/flash write byte enable. active low. 88 erwen1/ testreqb o external i/o and rom/sram/flash write byte enable. active low. 89 erwen0/ testack o external i/o and rom/sram/flash write byte enable. active low. 90 vdd-core p 1.8v digital core v dd . 91 vss-core gnd digital core v ss . 92 urxd i uart receive data. 93 udtrn/ dbgenn o uart data terminal ready. active low. /debug enable (factory test signal). 94 utxd o uart transmit data. note : 1. gnd = ground. p = power supply. i = input. o = output. i/o = bidirectional. o/i = output in normal mode; input pin during reset. nc = no connect.
micrel, inc. ks8695x june 2006 9 m9999-060106 pin number pin name type (1) pin function 95 udsrn i uart data set ready. active low. 96 urtsn/ cpuclksel o/i uart request to send/cpu clock select. 97 uctsn/ bisten i uart data set ready. active low. /bist enable (factory test signal). 98 udcdn/ scanen i uart data carrier detect. /scan enable (factory test signal). 99 urin/ tstrst i uart ring indicator/chip test reset (factory test signal). 100 gpio7 i/o general purpose i/o pin. 101 gpio6 i/o general purpose i/o pin. 102 gpio5/ tout1 i/o general purpose i/o pin/timer 1 output pin. 103 vdd-io p 3.3v digital i/o circuitry v dd . 104 vss-io gnd digital i/o v ss . 105 gpio4/ tout0 i/o general purpose i/o pin/timer 0 output pin. 106 gpio3/ eint3 i/o general purpose i/o pin/exte rnal interrupt request pin. 107 gpio2/ eint2 i/o general purpose i/o pin/exte rnal interrupt request pin. 108 gpio1/ eint1 i/o general purpose i/o pin/exte rnal interrupt request pin. 109 gpio0/ eint0 i/o general purpose i/o pin/exte rnal interrupt request pin. 110 tck i jtag test clock. 111 tms i jtag test mode select. 112 tdi i jtag test data in. 113 tdo o jtag test data out. 114 trstn i jtag test reset. active low. 115 vdd-core p 1.8v digital core v dd . 116 vss-core gnd digital core v ss . 117 testen i chip test enable (factory test signal). 118 wled1/ b0size1 o/i wan led programmable indicator 1/bank 0 size bit 1. 119 wled0/ b0size0 o/i wan led programmable indicator 0/bank 0 size bit 0. note : 1. gnd = ground. p = power supply. i = input. o = output. i/o = bidirectional. o/i = output in normal mode; input pin during reset.
micrel, inc. ks8695x june 2006 10 m9999-060106 pin number pin name type (1) pin function 120 l4led1/ dbgad7 o lan port 4 led programmable indicator 1. 121 l4led0/ dbgad6 o lan port 4 led programmable indicator 0. 122 l3led1/ dbgad5 o lan port 3 led programmable indicator 1. 123 l3led0/ dbgad4 o lan port 3 led programmable indicator 0. 124 l2led1/ dbgad3 o lan port 2 led programmable indicator 0. 125 l2led0/ dbgad2 o lan port 2 led programmable indicator 0. 126 l1led1/ dbgad1 o lan port 1 led programmable indicator 1. 127 l1led0/ dbgad0 o lan port 1 led programmable indicator 0. 128 vdd-core p 1.8v digital core v dd . 129 vss-core gnd digital core v ss . 130 test4 nc this pin must be left as no connect. 131 test5 nc this pin must be left as no connect. 132 test6 nc this pin must be left as no connect. 133 test7 nc this pin must be left as no connect. 134 test8 nc this pin must be left as no connect. 135 test9 nc this pin must be left as no connect. 136 test10 nc this pin must be left as no connect. 137 vdd-io p 3.3v digital i/o circuitry v dd . 138 vss-io gnd digital i/o v ss . 139 test11 nc this pin must be left as no connect. 140 test12 nc this pin must be left as no connect. 141 test13 nc this pin must be left as no connect. 142 test14 nc this pin must be left as no connect. 143 test15 nc this pin must be left as no connect. 144 test16 nc this pin must be left as no connect. 145 test17 nc this pin must be left as no connect. 146 test18 nc this pin must be left as no connect. note : 1. gnd = ground. p = power supply. o = output. nc = no connect.
micrel, inc. ks8695x june 2006 11 m9999-060106 pin number pin name type (1) pin function 147 test19 nc this pin must be left as no connect. 148 resetn i ks8695x chip reset. active low. 149 test2 i phy test pin (factory test signal). 150 xclk1 i external clock in. 151 xclk2 i external clock in (negative polarity). 152 vdda-pll p 1.8v analog v dd for pll. 153 gnda gnd analog ground. 154 vddar p 1.8v analog v dd. 155 gnda gnd analog ground. 156 gnda gnd analog ground. 157 vddar p 1.8v analog v dd. 158 wanfxsd/ dout i/o wan fiber signal detect/dout:factory analog test mode. 159 wanrxp i wan phy receive signal + (differential). 160 wanrxm i wan phy receive signal ? (differential). 161 gnda gnd analog ground. 162 wantxm o wan phy transmit signal ? (differential). 163 wantxp o wan phy transmit signal + (differential). 164 gnda gnd analog ground. 165 lanrxp1 i lan port 1 phy receive signal + (differential). 166 lanrxm1 i lan port 1 phy receive signal ? (differential). 167 gnda gnd analog ground. 168 lantxm1 o lan port 1 phy transmit signal ? (differential). 169 lantxp1 o lan port 1 phy transmit signal + (differential). 170 vddar p 1.8v analog v dd. 171 gnda gnd analog ground. 172 iset i set phy transmit output current. connect to ground with 3.01k ? 1% resistor. 173 vddat p 2.5/3.3v analog v dd. 174 lanrxp2 i lan port 2 phy receive signal + (differential). 175 lanrxm2 i lan port 2 phy receive signal ? (differential). 176 gnda gnd analog ground. 177 lantxm2 o lan port 2 phy transmit signal ? (differential). 178 lantxp2 o lan port 2 phy transmit signal + (differential). note : 1. gnd = ground. p = power supply. i = input. o = output. i/o = bidirectional. nc = no connect.
micrel, inc. ks8695x june 2006 12 m9999-060106 pin number pin name type (1) pin function 179 vddat p 2.5v/3.3v analog v dd . 180 lanrxp3 i lan port 3 phy receive signal + (differential). 181 lanrxm3 i lan port 3 phy receive signal ? (differential). 182 gnda gnd analog ground. 183 lantxm3 o lan port 3 phy transmit signal ? (differential). 184 lantxp3 o lan port 3 phy transmit signal + (differential). 185 gnda gnd analog ground. 186 vddar p 1.8v analog v dd . 187 lanrxp4 i lan port 4 phy receive signal + (differential). 188 lanrxm4 i lan port 4 phy receive signal ? (differential). 189 gnda gnd analog ground. 190 lantxm4 o lan port 4 phy transmit signal ? (differential). 191 lantxp4 o lan port 4 phy transmit signal + (differential). 192 gnda gnd analog ground. 193 vddar p 1.8v analog v dd . 194 gnda gnd analog ground. 195 vddar p 1.8v analog v dd . 196 gnda gnd analog ground. 197 test1 i phy test pin (factory test signal). 198 addr19 o address bit. 199 addr18 o address bit. 200 addr17 o address bit. 201 addr16 o address bit. 202 addr15 o address bit. 203 addr14 o address bit. 204 addr13 o address bit. 205 addr21/ba1 o address bit/bank ad dress bit 1 for sdram interface. 206 addr20/ba0 o address bit/bank ad dress bit 0 for sdram interface. 207 addr12 o address bit. 208 addr11 o address bit. note : 1. gnd = ground. p = power supply. i = input. o = output.
micrel, inc. ks8695x june 2006 13 m9999-060106 pin configuration 1 vss_io vdd_io gpio5/tout1 gpio6 gpio7 urin/tstrst udcdn/scanen uctsn/bisten urtsn/cpuclksel udsrn utxd udtrn/dbgenn urxd vss_core vdd_core erwen0/testack erwen1/testreqb erwen2/testreqa erwen3/tictestenn eroen/wrstpls mpmsel wrsto rcsn0 rcsn1 vss_io vdd_io ewaitn ecsn0 ecsn1 ecsn2 vss_io vdd_io data0 data1 data2 data3 data4 data5 data6 data7 vss_io vdd_io data8 data9 data10 data11 data12 data13 data14 data15 vss_io vdd_io vddar wanfxsd/dout wanrxp wanrxm gnda wantxm wantxp gnda lanrxp1 lanrxm1 gnda lantxm1 lantxp1 vddar gnda iset vddat lanrxp2 lanrxm2 gnda lantxm2 lantxp2 vddat lanrxp3 lanrxm3 gnda lantxm3 lantxp3 gnda vddar lanrxp4 lanrxm4 gnda lantxm4 lantxp4 gnda vddar gnda vddar gnda test1 addr19 addr18 addr17 addr16 addr15 addr14 addr13 addr21/ba1 addr20/ba0 addr12 addr11 vdd_io vss_io addr10 addr9 addr8 addr7 addr6 addr5 addr4 addr3 vdd_io vss_io addr2 addr0 sdcsn1 sdcsn0 sdrasn sdcasn sdwen vdd_io vss_io sdoclk sdiclk vdd_core vss_core sdqm3 sdqm2 sdqm1 sdqm0 data31 data30 data29 vdd_io vss_io data28 data27 data26 data25 data24 data23 data22 vdd_core vss_core data21 data20 vdd_io vss_io data19 data18 data17 data16 gnda gnda vddar gnda vdda_pll xclk2 xclk1 test2 resetn test pin test pin test pin test pin test pin test pin vss_io vdd_io test pin test pin test pin test pin test pin test pin test pin vss_core vdd_core l1led0/dbgad0 l1led1/dbgad1 l2led0/dbgad2 l2led1/dbgad3 l3led0/dbgad4 l3led1/dbgad5 l4led0/dbgad6 l4led1/dbgad7 wled0/b0size0 wled1/b0size1 testen vss_core vdd_core trstn tdo tdi tms tck gpio0/eint0 gpio1/eint1 gpio2/eint2 gpio3/eint3 gpio4/tout0 52 104 156 test pin test pin test pin 208-pin pqfp (pq)
micrel, inc. ks8695x june 2006 14 m9999-060106 functional description introduction the centaur ks8695x is a cost-effective, high-performance r outer-on-a-chip solution for ethernet-based systems. it integrates a powerful processor with a 5- port switch that consists of five mac units, five physical layer transceivers (phys), dma engines, and hardware protocol engines for cpu off loading. the ks8695x is built around the 16/32-bit arm922t risc pr ocessor. the arm922t is a scalable, high-performance, microprocessor developed for highly int egrated system-on-a-chip applications. the ks8695x offers an 8kb i-cache and an 8kb d-cache to reduce memory access latency for high-performance applications. there are also sdram, sram, and rom interfaces with configurable bus speeds and data width. the ks8695x provides external i/o interfaces, a uart interface, ageneral purpose i/o, a jtag debugging port, an internal interrupt controller, and internal timers. the ks8695x contains independent dma engines for the wan and lan. each of the independent dma engines supports burst mode as well as little-endian byte ordering for memory buffers and descriptors. each dma engine contains one 3kb receive fifo and one 3kb transmit fifo to ensure back-t o-back packet reception and no under-runs on packet transmission. an integrated switch provides hardware support for some of the most desirable layer 2 features such as port-based vlan, qos/cos packet prioritization, igmp snooping, and sp anning tree protocol. the switch contains a 16kx32 sram on-chip memory for frame buffering. the embedded frame bu ffer memory is designed with a 1.4gbps on-chip memory bus. this allows the ks8695x to perform full non-blocking frame switching and/or routing. there are five mac units in the ks8695x: four are for lan and one is for the wan. connected to the lan and wan macs are five 10/100 phys . these phys use micrel?s patented low-power analog phy technology to achieve increased performance. the phy units also support the auto mdi/mdi -x feature. the lan phys support 10base-t and 100base-tx opera tion as per the ieee802. 3 standard. the wan ph y supports 10base-t, 100base-tx, and 100base-fx operation. the ks8695x combines proven phy, mac, and switch techno logy with protocol and dma engines, and the powerful arm922t processor to create a solution that saves bom cost s, board real-estate, and design time while providing outstanding performance for a vari ety of router applications. cpu features ? 166mhz arm922t risc processor core ? on-chip amba bus 2.0 interfaces ? 16-bit thumb programming to relax memory requirement ? 8kb i-cache and 8kb d-cache ? little-endian mode supported ? con gurable memory management unit ? supports reduced cpu and system clock speed for power saving advanced memory controller features ? supports glueless connection to two banks of rom/sram/f lash memory with programmable 8/16/32 bit data bus and programmable access timing ? supports glueless connection to two sdram banks with programmable 8/16/32 bit data bus and programmable ras/cas latency ? supports three external i/o banks with programmable 8/16/32 bit data bus and programmable access timing ? programmable system clock speed for power management direct memory access (dma) engines ? independent mac dma engine with programmable burst mode for wan port ? independent mac dma engine with programmable burst mode for lan ports ? supports little-endian byte ordering for memory buffers and descriptors ? contains large independent receive and transmit fifos (3 kb receive/3kb transmit) for ba ck-to-back pack et receive, and guaranteed no under-run packet transmit ? data alignment logic and scatter gather capability
micrel, inc. ks8695x june 2006 15 m9999-060106 xcelerouter technology ? supports ipv4 ip header/tcp/udp packet ch ecksum generation for host cpu off loading ? supports ipv4 packet filtering based on checksum errors switch engine ? 5-port 10/100 integrated switch with one wa n and four lan physical layer transceivers ? 16kx32 on-chip sram for frame buffering ? 1.4gbps on-chip memory bandwidth for wire-speed frame switching ? 10mbps, 100mbps modes of operations for both full and half duplex ? supports port-based vlan ? support diffserv priority , ieee 802.1p-based priority or port-based priority ? integrated address look-up engine, s upports 1k absolute mac addresses ? automatic address learning, addr ess aging, and address migration ? broadcast storm protection ? full-duplex ieee 802.3x flow control ? half-duplex back pres sure flow control ? supports igmp snooping ? spanning tree protocol support network interface ? features five mac units and five phy units ? supports 10base-t and 100base-tx on all lan ports an d wan port. also supports 100base-fx on wan port ? supports automatic crc generation and checking ? supports automatic error packet discard ? supports ieee 802.3 auto-negotiation algor ithm of full-duplex and half-duple x operation for 10mbps and 100mbps ? supports full-/half-duplex operation on phy interfaces ? fully compliant with ieee 802.3 ethernet standards ? ieee 802.3 full-duplex flow control and half- duplex backpressure collision flow control ? supports mdi/mdi-x auto-crossover peripherals ? twenty-eight interrupt sources, incl uding four external interrupt sources ? normal or fast interrupt mode (irq, fiq) supported ? prioritized interrupt handling ? eight programmable general purpose i/o. pins individually configurable to input, output, or i/o mode for dedicated signals ? two programmable 32-bit timers with watchdog timer capability ? high-speed uart interface up to 115kbps other features ? integrated pll to generate cpu and system clocks ? jtag development interface for ice connection ? 208-pin pqfp
micrel, inc. ks8695x june 2006 16 m9999-060106 signal description system level hardware interfaces figure 2. system level interfaces at the system level the ks8695x f eatures the following interfaces: ? clock interface for crysta l or external oscillator ? jtag development interface ? one wan ethernet physical interface ? four lan ethernet physical interfaces ? phy led drivers ? one high-speed uart interface ? eight gpio pins ? advanced memory interface ? programmable synchronous bus rate ? programmable asynchronous interface timing ? independently programmable data bus wi dth for static and synchronous memory ? glueless connection to sdram ? glueless connection to ash memory or rom ? factory test ? power and ground configuration pins the following pins are sampled as input during reset. configuration pin name pin # setting bank0 flash data width b0size[1:0] 118, 119 ?00?= reserved ?01? = byte wide ?10? = half word wide (16 bits) ?11? = word wide (32 bits) wrsto polarity eroen/wrstpls 85 ?0? = active high ?1? = active low cpu clock select urtsn/cpuclksel 96 ?0? = normal mode (pll) '1? = bypass internal pll table 1. configuration pins
micrel, inc. ks8695x june 2006 17 m9999-060106 reset the ks8695x has a single reset input that can be driven by a sy stem reset circuit or a simple power on reset circuit. the ks8695x also features a reset output (wrsto) that can be used to reset other devices in the system. wrsto can be configured as either an active high reset or an active low re set through a strap-in option on pin 85 as shown in table 1. the ks8695x also has a built in watchdog timer. once t he user programs the watchdog timer and the timer setting expires, the ks8695x will reset itself and also assert wrst o to reset the other devices in the system. figure 3 shows a typical system that uses the ks 8695x wrsto as the system reset. figure 3. example of a reset circuit system clock the clock to the ks8695x can be supplied by either a 25mhz 50ppm crystal or by an oscillator. if an osc illator is used it shall be connected to the x1 input (pin 150) on the ks8695x. if a crystal is used, it shall be connected with a circuit like the one shown below. the 25mhz input clock is used by an internal pll to generate the programmable sdoclk. sdoclk is the system clock, and can be programmed fr om 25mhz to 125mhz using system clock and bus control register at offset 0x0004. the cpuclksel strap-in opti on on pin 96 needs to be pull ed low for norma l operation. figure 4. typical clock circuit
micrel, inc. ks8695x june 2006 18 m9999-060106 signal descriptions by group clock and reset pins pin name i/o type (1) description 150 xclk1/ cpuclk i external clock in. this signal is used as the source clock for the transmit clock of the internal mac and phy. the clock frequency should be 25mhz 50ppm. the xclk1 signal is also used as the reference clock signal for the internal pll togenerate the 125mhz internal system clock. cpuclk: factory clock test input when the internal pll is disabled (factory test signal). 151 xclk2 i external clock in. used with xclk1 pin when another polarity of crystal is needed. this is unused for a normal clock input. 96 urtsn/ cpuclksel o/i normal mode: uart request to send. active low output. during reset: cpu clock select. select cpu clock source. cpuclksel=0 (normal mode), the internal pll clock output is used as the cpu clock source. cpuclksel=1 (factory test signal): the external clock to the cpuclk pin is used as the internal cpu clock source. 148 resetn i ks8695x chip reset. active low input asserted for at least 256 system clock (40ns) cycles to reset the ks8695x. when in the reset state, all the output pins are tri- stated and all open drain signals are floating. 83 wrsto o watchdog timer reset output. this signal is asserted for at least 200ms if resetn is asserted or when the internal watchdog timer expires. 85 eroen/ wrstpls o/i normal mode: rom/sram/flash and external i/o output enable. active low. when asserted, this signal controls the output enable port of the specified device. during reset: watchdog timer reset polarity setting. wrstpls=0, active high; wrstpls=1, active low. no default. jtag interface pins pin name i/o type (1) description 110 tck i jtag test clock. 111 tms i jtag test mode select. 112 tdi i jtag test data in. 113 tdo o jtag test data out. 114 trstn i jtag test reset. active low. wan ethernet physical interface pins pin name i/o type (1) description 159 wanrxp i wan phy receive signal + (differential). 160 wanrxm i wan phy receive signal ? (differential). 162 wantxm o wan phy transmit signal ? (differential). 163 wantxp o wan phy transmit signal + (differential). 158 wanfxsd/ dout i/o wan fiber signal detect. signal detect input when the wan port is operated in 100base-fx 100mb fiber mode. dout:factory analog test mode. note : 1. i = input. o = output. i/o = bidirectional. o/i = output in normal mode; input pin during reset.
micrel, inc. ks8695x june 2006 19 m9999-060106 lan ethernet physical interface pins pin name i/o type (1) description 187 180 174 165 lanrxp[4:1] i lan port[4:1] phy receive signal + (differential). 188 181 175 166 lanrxm[4:1] i lan port[4:1] phy receive signal - (differential). 191 184 178 169 lantxp[4:1] o lan port[4:1] phy transmit signal + (differential). 190 183 177 168 lantxm[4:1] o lan port[4:1] phy transmit signal - (differential). 172 iset i set phy transmit output current. connect to ground through a 3.01k ? 1% resistor. phy led drivers pin name i/o type (1) description 119 wled0/ b0size0 o/i normal mode: wan led indicator 0. programmable via wan misc. control register bits [2:0]. ?000? = speed; ?001? = link; ?010? = full/half duplex; ?011? = collision; ?100? = tx/rx activity; ?101? = full-duplex collision; ?110? = link/activity. during reset: bank 0 data access size. bank 0 is used for the boot program. b0size[1:0] are used to specify the size of the bank 0 data bus width as follows: ?01? = one byte, ?10? = half-word, ?11? = one word, and ?00? = reserved. 118 wled1/ b0size1 o/i normal mode: wan led indicator 1. programmable via wan misc. control register bits [6:4]. ?000? = speed; ?001?= link; ?010? = full/half duplex; ?011? = collision; ?100? = tx/rx activity; ?101? = full-duplex collision; ?110? = link/activity. during reset: bank 0 data access size. bank 0 is used for the boot program. b0size[1:0] are used to specify the size of the bank 0 data bus width as follows: ?01?= one byte, ?10? = half-word, ?11? = one word, and ?00? = reserved. 121 123 125 127 l[4:1]led0 o lan port[4:1] led indicator 0. programmable via switch control 0 register bits [27:25]. ?000? = speed; ?001? = link; ?010? = full/half duplex; ?011? = collision; ?100? = tx/rx activity; ?101? = full-duplex collision; ?110? = link/activity. 120 122 124 126 l[4:1]led1 o lan port[4:1] led indicator 1. programmable via switch control 0 register bits [24:22]. ?000? = speed; ?001? = link; ?010? = full/half duplex; ?011? = collision; ?100? = tx/rx activity; ?101? = full-duplex collision; ?110? = link/activity. note : 1. i = input. o = output. o/i = output in normal mode; input pin during reset.
micrel, inc. ks8695x june 2006 20 m9999-060106 uart pins pin name i/o type (1) description 92 urxd i uart receive data. 94 utxd o uart transmit data. 93 udtrn/ dbgenn o uart data terminal ready. active low. debug enable (factory test signal). 95 udsrn i uart data set ready. active low. 96 urtsn/ cpuclksel o/i normal mode: uart request to send. active low output. during reset: cpu clock select. select cpu clock source. cpuclksel=0 (normal mode), the internal pll clock output is used as the cpu clock source. cpuclksel=1 (factory test signal), the external clock to the cpuclk pin is used as the internal cpu clock source. 97 uctsn/ bisten i uart clear to send. bist enable (factory test signal). 98 udcdn/ scanen i uart data carrier detect. scan enable (factory test signal). 99 urin/ tstrst i uart ring indicator. chip test reset (factory test signal). general purpose i/o pins pin name i/o type (1) description 109 gpio0/ eint0 i/o general purpose i/o pin/external interrupt request pin. 108 gpio1/ eint1 i/o general purpose i/o pin/external interrupt request pin. 107 gpio2/ eint2 i/o general purpose i/o pin/external interrupt request pin. 106 gpio3/ eint3 i/o general purpose i/o pin/external interrupt request pin. 105 gpio4/ tout0 i/o general purpose i/o pin/timer 0 output pin. 102 gpio5/ tout1 i/o general purpose i/o pin/timer 1 output pin. 101 gpio6 i/o general purpose i/o pin. 100 gpio7 i/o general purpose i/o pin. note : 1. i = input. o = output. i/o = bidirectional. o/i = output in normal mode; input pin during reset.
micrel, inc. ks8695x june 2006 21 m9999-060106 resered pins pin name i/o type (1) description 84 test3 nc the reserved pins serve as no connect in order to ensure correct operation of the device. do not connect any signal to these pins. 130 test4 nc no connect. 131 test5 nc no connect. 132 test6 nc no connect. 133 test7 nc no connect. 134 test8 nc no connect. 135 test9 nc no connect. 136 test10 nc no connect. 139 test11 nc no connect. 140 test12 nc no connect. 141 test13 nc no connect. 142 test14 nc no connect. 143 test15 nc no connect. 144 test16 nc no connect. 145 test17 nc no connect. 146 test18 nc no connect. 147 test19 nc no connect. advanced memory interface (sdram/rom/flash/sram/external i/o) pin name i/o type (1) description 24 sdiclk i sdram clock in: sdram clock input for the sdram memory controller interface. 23 sdoclk o system/sdram clock out: output of the internal system clock, it is also used as the clock signal for sdram interface. 205 addr21/ba1 o address bit 21/bank address input 1: address bit 21 for asynchronous accesses. bank address input bit 1 for sdram accesses. 206 addr20/ba0 o address bit 20/bank address input 0: address bit 20 for asynchronous accesses. bank address input bit 0 for sdram accesses. 198 199 200 201 202 203 204 207 208 3 4 5 6 7 8 9 10 13 14 15 addr[19] addr[18] addr[17] addr[16] addr[15] addr[14] addr[13] addr[12] addr[11] addr[10] addr[9] addr[8] addr[7] addr[6] addr[5] addr[4] addr[3] addr[2] addr[1] addr[0] o address bus: the 22-bit address bus (including addr[21:20] above) covers 4m word memory space shared by rom/sram/flash, sdram, and external i/o banks. during the sdram cycles, the internal address bus is used to generate ras and cas addresses for the sdram. the number of column address bits in the sdram banks can be programmed from 8 to 11 bits via the sdram control registers. addr[12:0] are the sdram address, and addr[21:20] are the sdram bank address. during other cycles, the addr[21:0] is the byte address of the data transfer. note: the address pinout non-sequential by design. it is optimized for board level connections to sdram. for sdram and rom/sram/flash, connect addr[0] to a0 on the memory, addr[1] to a1 on the memory, and so forth. address bit mapping for 8-bit, 16-bit, 32-bit access. for external i/o devices, the system designer must connect address lines conventionally for 8-bit, 16-bit, and 32-bit access. note : 1. i = input. o = output. nc = no connect.
micrel, inc. ks8695x june 2006 22 m9999-060106 advanced memory interface (sdram/rom /flash/sram/externa l i/o) (continued) pin name i/o type (1) description 31 32 33 36 37 38 39 40 41 42 45 46 49 50 51 52 55 56 57 58 59 60 61 62 65 66 67 68 69 70 71 72 data[31] data[30] data[29] data[28] data[27] data[26] data[25] data[24] data[23] data[22] data[21] data[20] data[19] data[18] data[17] data[16] data[15] data[14] data[13] data[12] data[11] data[10] data[9] data[8] data[7] data[6] data[5] data[4] data[3] data[2] data[1] data[0] i/o external data bus. 32-bit bidirectional data bus for data transfer. ks8695x also supports 8- and 16-bit data bus widths. 16 17 sdcsn[1] sdcsn[0] o sdram chip select: active low chip select pins for sdram. the ks8695x supports up to two sdram banks. one sdcsn output is provided for each bank. 18 sdrasn o sdram row address strobe: active low. the row address strobe pin for sdram. 19 sdcasn o sdram column address strobe: active low. the column address strobe pin for sdram. 20 sdwen o sdram write enable: active lo w. the write enable signal for sdram. 27 28 29 30 sdqm[3] sdqm[2] sdqm[1] sdqm[0] o sdram data input/output mask: data input/output mask signals for sdram. the sdqm is sampled high and is an output mask signal for write accesses and an output enable signal for read accesses. input data are masked during a write cycle. the sdqm0/1/2/3 correspond to xdata[ 7:0], xdata[15:8], xdata[23:16] and xdata[31:24], respectively. 75 76 77 ecsn[2] ecsn[1] ecsn[0] o external i/o device chip select: active low. three external i/o banks are provided for external memory mapped i/o operations. each i/o bank stores up to 16kb. the ecsnx signals indicate which of the three i/o banks is selected. note : 1. o = output. i/o = bidirectional.
micrel, inc. ks8695x june 2006 23 m9999-060106 advanced memory interface (sdram/rom /flash/sram/externa l i/o) (continued) pin name i/o type (1) description 78 ewaitn i external wait: active low. this signal is asserted when an external i/o device or a rom/sram/flash bank needs more access cycles than those defined in the corresponding control register. 81 82 rcsn[1] rcsn[0] o rom/sram/flash chip select: active low. the ks8695x can access up to two external rom/sram/flash memory banks. the rcsn pins can be controlled to map the cpu addresses into physical memory banks. 85 eroen/ wrstpls o/i normal mode: external i/o and rom/sram/flash output enable:active low. when asserted, this signal controls the output enable port of the specified memory device. during reset: watchdog timer reset polarity setting. wrstpls=0, active low; wrstpls = 1, active high. no default. 89 erwen0/ testack o external i/o and rom/sram/flash write byte enable: active low. when asserted, the erwenx controls the byte write enable of the memory device (except sdram). arm cpu test signal (factory test signal). 88 erwen1/ testreqb o external i/o and rom/sram/flash write byte enable: active low. when asserted, the erwenx controls the byte write enable of the memory device (except sdram). arm cpu test signal (factory test signal). 87 erwen2/ testreqa o external i/o and rom/sram/flash write byte enable: active low. when asserted, the erwenx controls the byte write enable of the memory device except sdram). arm cpu test signal (factory test signal). 86 erwen3/ tictestenn o external i/o and rom/sram/flash write byte enable. active low. when asserted, the erwenx controls the byte write enable of the memory device (except sdram). arm cpu test signal (factory test signal). 119 wled0/ b0size0 o/i normal mode: wan led indicator 0:programmable via wan misc. control register bits [2:0]. 000 = speed; 001 = link; 010 = full/half duplex; 011 = collision; 100 = tx/rx activity; 101 = full-duplex collision; 110 = link/activity. during reset: bank 0 data access size. bank 0 is used for the boot program. b0size[1:0] are used to specify the size of the bank 0 data bus width as follows: ?01? = one byte, ?10? = half-word, ?11? = one word, and ?00? = reserved. 118 wled1/ b0size1 o/i normal mode: wan led indicator 1:progra mmable via wan misc. control register bits [6:4]. 000 = speed; 001 = link; 010 = full/half duplex; 011 = collision; 100 = tx/rx activity; 101 = full-duplex collision; 110 = link/activity. during reset: bank 0 data access size. bank 0 is used for the boot program. b0size[1:0] are used to specify the size of the bank 0 data bus width as follows: ?01? = one byte, ?10? = half-word, ?11? = one word, and ?00? = reserved. factory test pins pin name i/o type (1) description 117 testen i chip test enable: (factory test signal), pull down if not used. 197 test1 i phy test pin: (factory test signal). 149 test2 i phy test pin: (factory test signal). note : 1. i = input. o = output. o/i = output in normal mode; input pin during reset.
micrel, inc. ks8695x june 2006 24 m9999-060106 power and ground pins pin name i/o type (1) description 152 vdda-pll p 1.8v analog v dd for pll. 173 179 vddat p 2.5v/3.3v analog v dd . these pins can use voltage of either 2.5v or 3.3v. 154 157 170 186 193 195 vddar p 1.8v analog v dd . 25 43 90 115 128 vdd-core p 1.8v digital core v dd . 1 11 21 34 47 53 63 73 79 103 137 vdd-io p 3.3v digital i/o circuitry v dd . 26 44 91 116 129 vss-core gnd digital core v ss . 2 12 22 35 48 54 64 74 80 104 138 vss-io gnd digital i/o v ss . note : 1. p = power supply. gnd = ground.
micrel, inc. ks8695x june 2006 25 m9999-060106 power and ground pins (continued) pin name i/o type (1) description 153 155 156 161 164 167 171 176 182 185 189 192 194 196 gnda gnd analog ground. note : 1. gnd = ground.
micrel, inc. ks8695x june 2006 26 m9999-060106 address map and register description memory map upon power up, the ks8695x memory map is configured as shown below. address range region description 0x03ff0000-0x03ffffff 64kb ks8695px system con guration register space 0x02000000-0x03feffff 32mb not con gured 0x00000000-0x01ffffff 32mb flash bank 0 memory map example the default base address for the ks8695x sy stem configuration registers is 0x03ff 0000. after power up, the user is free to remap the memory for their specific application. the following is an example of the memory space remapped for operation. address range region description 0x03ff0000-0x03ffffff 64kb ks8695px system con guration register space 0x02900000-0x03feffff 23mb spare (external i/o) 0x02100000-0x028fffff 8mb flash 0x00100000-0x020fffff 32mb sdram 0x00000000-0x0007ffff 512kb sram register description the ks8695x system configuration registers (scrs) are locate d in a block of 64kb in the host memory address space. after power up and initialization, the user can remap the scrs to a desired offset. the scrs are 32 bits wide. they are 32 bit word-aligned and must be accessed using word instru ctions. a description of the ks8695x system configuration registers follows. for bit definitions, please s ee the detailed "register description" section. address description mode size system registers 0x0000 system configuration register r/w [31:0] 0x0004 system clock and bus control register r/w [31:0] memory controller interface registers 0x4000 external i/o access control register 0 r/w [31:0] 0x4004 external i/o access control register 1 r/w [31:0] 0x4008 external i/o access control register 2 r/w [31:0] 0x4010 rom/sram/flash control register 0 r/w [31:0] 0x4014 rom/sram/flash control register 1 r/w [31:0] 0x4020 rom/sram/flash general register r/w [31:0] 0x4030 sdram control register 0 r/w [31:0] 0x4034 sdram control register 1 r/w [31:0] 0x4038 sdram general control register r/w [31:0] 0x403c sdram buffer control register r/w [31:0] 0x4040 sdram refresh timer register r/w [31:0]
micrel, inc. ks8695x june 2006 27 m9999-060106 address description mode size wan dma registers 0x6000 wan mac dma transmit control register r/w [31:0] 0x6004 wan mac dma receive control register r/w [31:0] 0x6008 wan mac dma transmit start command register r/w [31:0] 0x600c wan mac dma receive start command register r/w [31:0] 0x6010 wan transmit descriptor list base address register r/w [31:0] 0x6014 wan receive descriptor list base address register r/w [31:0] 0x6018 wan mac station address low register r/w [31:0] 0x601c wan mac station address high register r/w [31:0] 0x6080 wan mac additional station address low register 0 r/w [31:0] 0x6084 wan mac additional station address high register 0 r/w [31:0] 0x6088 wan mac additional station address low register 1 r/w [31:0] 0x608c wan mac additional station address high register 1 r/w [31:0] 0x6090 wan mac additional station address low register 2 r/w [31:0] 0x6094 wan mac additional station address high register 2 r/w [31:0] 0x6098 wan mac additional station address low register 3 r/w [31:0] 0x609c wan mac additional station address high register 3 r/w [31:0] 0x60a0 wan mac additional station address low register 4 r/w [31:0] 0x60a4 wan mac additional station address high register 4 r/w [31:0] 0x60a8 wan mac additional station address low register 5 r/w [31:0] 0x60ac wan mac additional station address high register 5 r/w [31:0] 0x60b0 wan mac additional station address low register 6 r/w [31:0] 0x60b4 wan mac additional station address high register 6 r/w [31:0] 0x60b8 wan mac additional station address low register 7 r/w [31:0] 0x60bc wan mac additional station address high register 7 r/w [31:0] 0x60c0 wan mac additional station address low register 8 r/w [31:0] 0x60c4 wan mac additional station address high register 8 r/w [31:0] 0x60c8 wan mac additional station address low register 9 r/w [31:0] 0x60cc wan mac additional station address high register 9 r/w [31:0] 0x60d0 wan mac additional station address low register 10 r/w [31:0] 0x60d4 wan mac additional station address high register 10 r/w [31:0] 0x60d8 wan mac additional station address low register 11 r/w [31:0] 0x60dc wan mac additional station address high register 11 r/w [31:0] 0x60e0 wan mac additional station address low register 12 r/w [31:0] 0x60e4 wan mac additional station address high register 12 r/w [31:0] 0x60e8 wan mac additional station address low register 13 r/w [31:0] 0x60ec wan mac additional station address high register 13 r/w [31:0] 0x60f0 wan mac additional station address low register 14 r/w [31:0] 0x60f4 wan mac additional station address high register 14 r/w [31:0] 0x60f8 wan mac additional station address low register 15 r/w [31:0] 0x60fc wan mac additional station address high register 15 r/w [31:0]
micrel, inc. ks8695x june 2006 28 m9999-060106 address description mode size lan dma registers 0x8000 lan mac dma transmit control register r/w [31:0] 0x8004 lan mac dma receive control register r/w [31:0] 0x8008 lan mac dma transmit start command register r/w [31:0] 0x8010 lan transmit descriptor list base address r/w [31:0] 0x8014 lan receive descriptor list base address r/w [31:0] 0x8018 lan mac station address low register r/w [31:0] 0x801c lan mac station address high register r/w [31:0] 0x8080 lan mac additional station address register low 0 r/w [31:0] 0x8084 lan mac additional station address register high 0 r/w [31:0] 0x8088 lan mac additional station address register low 1 r/w [31:0] 0x808c lan mac additional station address register high 1 r/w [31:0] 0x8090 lan mac additional station address register low 2 r/w [31:0] 0x8094 lan mac additional station address register high 2 r/w [31:0] 0x8098 lan mac additional station address register low 3 r/w [31:0] 0x809c lan mac additional station address register high 3 r/w [31:0] 0x80a0 lan mac additional station address register low 4 r/w [31:0] 0x80a4 lan mac additional station address register high 4 r/w [31:0] 0x80a8 lan mac additional station address register low 5 r/w [31:0] 0x80ac lan mac additional station address register high 5 r/w [31:0] 0x80b0 lan mac additional station address register low 6 r/w [31:0] 0x80b4 lan mac additional station address register high 6 r/w [31:0] 0x80b8 lan mac additional station address register low 7 r/w [31:0] 0x80bc lan mac additional station address register high 7 r/w [31:0] 0x80c0 lan mac additional station address register low 8 r/w [31:0] 0x80c4 lan mac additional station address register high 8 r/w [31:0] 0x80c8 lan mac additional station address register low 9 r/w [31:0] 0x80cc lan mac additional station address register high 9 r/w [31:0] 0x80d0 lan mac additional station address register low 10 r/w [31:0] 0x80d4 lan mac additional station address register high 10 r/w [31:0] 0x80d8 lan mac additional station address register low 11 r/w [31:0] 0x80dc lan mac additional station address register high 11 r/w [31:0] 0x80e0 lan mac additional station address register low 12 r/w [31:0] 0x80e4 lan mac additional station address register high 12 r/w [31:0] 0x80e8 lan mac additional station address register low 13 r/w [31:0] 0x80ec lan mac additional station address register high 13 r/w [31:0] 0x80f0 lan mac additional station address register low 14 r/w [31:0] 0x80f4 lan mac additional station address register high 14 r/w [31:0] 0x80f8 lan mac additional station address register low 15 r/w [31:0] 0x80fc lan mac additional station address register high 15 r/w [31:0]
micrel, inc. ks8695x june 2006 29 m9999-060106 address description mode size uart registers 0xe000 uart receive buffer register r/w [31:0] 0xe004 uart transmit holding register r/w [31:0] 0xe008 uart fifo control register r/w [31:0] 0xe00c uart line control register r/w [31:0] 0xe010 uart modem control register r/w [31:0] 0xe014 uart line status register r/w [31:0] 0xe018 uart modem status register r/w [31:0] 0xe01c uart baud rate divisor register r/w [31:0] 0xe020 uart status register r/w [31:0] interrupt controller registers 0xe200 interrupt mode control register r/w [31:0] 0xe204 interrupt enable register r/w [31:0] 0xe208 interrupt status register r/w [31:0] 0xe210 not used na na 0xe20c interrupt priority register for wan mac r/w [31:0] 0xe214 interrupt priority register for lan mac r/w [31:0] 0xe218 interrupt priority register for timer r/w [31:0] 0xe21c interrupt priority register for uart r/w [31:0] 0xe220 interrupt priority register for external interrupt r/w [31:0] 0xe224 interrupt priority register for communications channel r/w [31:0] 0xe228 interrupt bus error response register r/w [31:0] 0xe22c interrupt mask status register r/w [31:0] 0xe230 interrupt pending highest priority register for fiq r/w [31:0] 0xe234 interrupt pending highest priority register for irq r/w [31:0] timer registers 0xe400 timer control register r/w [31:0] 0xe404 timer 1 timeout count register r/w [31:0] 0xe408 timer 0 timeout count register r/w [31:0] 0xe40c timer 1 pulse count register r/w [31:0] 0xe410 timer 0 pulse count register r/w [31:0] general purpose i/o registers 0xe600 i/o port mode register r/w [31:0] 0xe604 i/o port control register r/w [31:0] 0xe608 i/o port data register r/w [31:0]
micrel, inc. ks8695x june 2006 30 m9999-060106 address description mode size switch engine configuration registers 0xe800 switch engine control 0 register r/w [31:0] 0xe804 switch engine control 1 register r/w [31:0] 0xe808 port 1 configuration register r/w [31:0] 0xe80c port 2 configuration register r/w [31:0] 0xe810 port 3 configuration register r/w [31:0] 0xe814 port 4 configuration register r/w [31:0] 0xe818 port 5 configuration register r/w [31:0] 0xe81c ports 1 and 2 auto negotiation (an) register r/w [31:0] 0xe820 ports 3 and 4 auto negotiation (an) register r/w [31:0] 0xe824 look-up engine (lue) control register r/w [31:0] 0xe828 look-up engine (lue) indirect register high r/w [31:0] 0xe82c look-up engine (lue) indirect register low r/w [31:0] 0xe830 advance feature control register r/w [31:0] 0xe834 dscp register high r/w [31:0] 0xe838 dscp register low r/w [31:0] 0xe83c switch engine mac address register high r/w [31:0] 0xe840 switch engine mac address register low r/w [31:0] 0xe844 management counter indirect access register r/w [31:0] 0xe848 management counter data register r/w [31:0] 0xe84c ports 1 and 2 phy power management r/w [31:0] 0xe850 ports 3 and 4 phy power management r/w [31:0] miscellaneous registers 0xea00 device id register r/w [31:0] 0xea04 revision id register r/w [31:0] 0xea08 not used na na 0xea0c wan miscellaneous control register r/w [31:0] 0xea10 wan phy power management register r/w [31:0]
micrel, inc. ks8695x june 2006 31 m9999-060106 absolute maximum ratings (1) supply voltage (v ddar ,v dda_pll ,v dd_core )....................... ?0.5v to +2.4v (v ddat ,v dd_io ). ........................................ ?0.5v to +4.0v input voltage (all input s) .............................. ?0.5v to +4.0v output voltage (all outputs) ......................... ?0.5v to +4.0v lead temperature (solde ring, 10sec .)....................... 270c pb (lead) free temperatur e (soldering, 10sec.)....... 260c storage temperature (t s ) .........................?55c to +150c operating ratings (2) supply voltage (v ddar ,v dda_pll ,v dd_core )....................... +1.7v to +1.9v (v ddat ) (3) ................................................. +2.4v to +2.6v (v ddat ) (3) ......................................... +3.135v to +3.456v (v dd_io )................................................... +3.0v to +3.6v ambient temperature (t a ) ............................ ?0c to +70c junction temperature (t j ) ......................................... 150c package thermal resistance (4) pqfp ( ja ) no air fl ow ..................................39. 1c/w electrical characteristics (5) symbol parameter condition min typ max units total supply current (including tx output driver current) 100base-tx operation: all ports 100% utilization, sdoclk = 125mhz i dx 100base-tx (analog i/o) v ddat = +2.5v or +3.3v 0.220 a i rx , i ddc 100base-tx (analog rx, digital core) v dda_pll , v ddar , v dd_core = +1.8v 0.223 a i ddio 100base-t (digital i/o) v dd_io = +3.3v 0.164 a 10base-tx operation: all ports 100% utilization, sdoclk = 125mhz i dx 10base-tx (analog i/o) v ddat = +2.5v or +3.3v 0.165 a i rx , i ddc 10base-tx (analog rx, digital core) v dda_pll , v ddar , v dd_core = +1.8v 0.333 a i ddio 10base-t (digital i/o) v dd_io = +3.3v 0.133 a auto-negotiation mode: sdoclk = 125mhz i dx 10base-tx (analog i/o) v ddat = +2.5v or +3.3v 0.033 a i rx , i ddc 10base-tx (analog rx digital core) v dda_pll , v ddar , v dd_core = +1.8v 0.216 a i ddio 10base-t (digital i/o) v dd_io = +3.3v 0.118 a ttl inputs v ih input high voltage 2.0 v v il input low voltage 0.8 v i in input current (excluding pull-up/pull-down) v in = gnd = v dd_io ?10 10 a ttl outputs v oh output high voltage i oh = ?8ma 2.4 v v ol output low voltage i ol = 8ma +0.4 v i oz output tri-state leakage 10 a 100base-tx transmit (measured differentially after 1:1 transformer) v o peak differential output voltage 100 ? termination on the differ ential output 0.95 1.05 v v imb output voltage imbalance 100 ? termination on the differential output 2 % rise/fall time rise/fall time imbalance 3 0 5 0.5 ns ns duty cycle distortion 0.5 ns t r , t t overshoot 5 % reference voltage of iset 0.5 v v set output jitters peak-to-peak 0.7 1.4 ns
micrel, inc. ks8695x june 2006 32 m9999-060106 symbol parameter condition min typ max units 10base-tx receive v sq squelch threshold 5mhz square wave 400 mv 10base-tx transmit (measured differentially after 1:1 transformer) v ddat = 2.5v peak differential output voltage 100 ? termination on the differ ential output 2.3 v jitters added 100 ? termination on the differential output 3.5 ns v p rise/fall time 28 30 ns notes: 1. exceeding the absolute maxi mum rating may damage the device. 2. the device is not guaranteed to function outside its operating rating. unused inputs must always be tied to an appropriate logic voltage level (ground to v dd ). 3. v ddat can operate from either a 2.5v or 3.3v supply. 4. no heat spreader in package. 5. specification for packaged product only.
micrel, inc. ks8695x june 2006 33 m9999-060106 ldo options for a standalone soho system using the ks8695x, micrel recommends the following low-cost ldo bundle: ? one mic5209bm for the +1.8v digital supply (v dd_core ) ? one mic5209-3.3bs for the +3.3v digital i/o supply (v dd_io ) and analog transmit supply (v ddat ) since each system may have a different power requirement, be su re to contact your micrel sales representative or field application engineer to help you find a cost -effective ldo solution for your project. figure 5. low-cost ldo option
micrel, inc. ks8695x june 2006 34 m9999-060106 timing diagrams trc tch tcs tsr suppl y voltages resetn strap-in strap-in pin output figure 6. reset timing symbol parameter min typ max units t sr stable supply voltages to reset high 10 ms t cs con guration set-up time 50 ns t ch con guration hold time 50 ns t rc reset to strap-in pin output 50 s table 2. reset timing parameters
micrel, inc. ks8695x june 2006 35 m9999-060106 figure 7. static/flash memory read cycle figure 8. static/flash memory write cycle symbol parameter min typ max units t cta valid address to cs setup time 0.8 1.1 1.3 ns t cos oe valid to cs setup time 0.6 0.6 1.0 ns t aac address access time rbitacc +1.0 rbitacc ns t dsu valid read data to oe setup time 2.0 ns t cws cs valid to we setup time 0.6 0.6 1.0 ns t cah address to cs hold time 1.0 1.0 1.4 ns t ocs rising edge oe to cs hold time 0 ns t oew oe pulsewidth rbitacc rbitacc rbitacc ns t wcs rising edge we to oe hold time 0 ns table 3. static/flash memory timing parameters symbol parameter (1) registers rbitacc programmable bank i access time 0x4010, 0x4014 table 4. programmable stat ic memory timing parameters note: 1. "i" refers to chip select parameters 0 and 1.
micrel, inc. ks8695x june 2006 36 m9999-060106 figure 9. external i/o read and write cycles symbol parameter min (1) typ (1) max (1) units t cta valid address to cs setup ebitacs +0.8 ebitacs +1.1 ebitacs +1.3 ns t cos cs valid to oe setup time ebitcos +0.6 ebitcos +0.6 ebitcos +1.0 ns t dsu valid read data to oe setup time 2.0 ns t cws cs valid to we setup time ebitcos +0.6 ebitcos +0.6 ebitcos +1.0 ns t dh cs to write data hold time 0 ns t cah cs to addr hold time ebitcoh +1.0 ebitcoh +1.0 ebitcoh +1.4 ns t oew oe/we pulsewidth ebitact ebitact ns t ocs , t csw rising edge oe/we to cs hold time 0 ns table 5. external i/o memory timing parameters note: 1. measurements for minimum were taken at 0c, typical at 25c, and maximum at 100c. symbol parameter (1) registers ebitacs programmable bank i address setup time before chip select 0x4000, 0x4004, 0x4008 ebitact programmable bank i write enable/output enable access time 0x4000, 0x4004, 0x4008 ebitcos programmable bank i chip select setup time before oen 0x4000, 0x4004, 0x4008 ebitcoh programmable bank i chip select hold time 0x4000, 0x4004, 0x4008 table 6. programmable ex ternal i/o timing parameters note: 1. "i" refers to chip select parameters 0, 1, or 2.
micrel, inc. ks8695x june 2006 37 m9999-060106 figure 10. sdram read timing figure 11. sdram write timing symbol parameter registers sdtrc programmable sdram ras to cas latency 0x4038 sdcas programmable sdram cas latency 0x4038 table 7. sdram timing parameters
micrel, inc. ks8695x june 2006 38 m9999-060106 symbol parameter min typ max units sdram signals rise time sdr clock rise time 4.2 4.0 4.8 ns sdr address rise time 3.8 4.4 4.8 ns sdr bank select rise time 3.6 4.2 4.4 ns sdr data rise time ns sdr chip select rise time 3.0 3.0 3.7 ns sdr ras rise time 3.4 3.6 3.8 ns sdr cas rise time 3.0 3.5 3.4 ns sdr we rise time 3.0 3.8 3.8 ns sdr dqm rise time 3.2 3.5 3.5 ns sdram signals fall time sdr clock fall time 5.0 6.0 6.4 ns sdr address fall time 4.4 5.4 5.5 ns sdr bank select fall time 5.2 5.5 6.0 ns sdr data fall time ns sdr chip select fall time 3.6 3.6 4.2 ns sdr ras fall time 3.8 3.8 4.4 ns sdr cas fall time 4.0 3.8 4.8 ns sdr we fall time 4.2 4.4 4.5 ns sdr dqm fall time 4.0 4.4 4.4 ns sdram timing specifications t01 clock-to-chip select out put delay 0.7 0.7 0.9 ns t11 clock-to-chip select ho ld time 0.7 0.6 0.6 ns t02 clock-to-address high-to-low 1.2 1.6 1.7 ns t12 clock-to-address low-to-high 1.3 1.5 1.6 ns t03 clock-to-bank select hi gh-to-low 1.9 1.8 1.9 ns t13 clock-to-bank select lo w-to-high 1.3 1.3 1.5 ns t04 clock-to-ras output de lay 1.1 1.1 1.5 ns t14 clock-to-ras hold time 1.1 0.9 1.3 ns t05 clock-to-cas output de lay 1.3 1.1 1.5 ns t15 clock-to-cas hold time 0.9 0.9 1.1 ns t06 clock-to-we output delay 1.1 1.3 1.5 ns t16 clock-to-we hold time 0.8 1.1 1.3 ns t07 clock-to-dqm output delay 0.7 1.1 1.1 ns t17 clock-to-dqm hold time 0.8 1.4 1.3 ns t08 clock-to-data output delay 0.4 0.6 0.8 ns t18 clock-to-data hold time 0.1 0.4 0.6 ns table 8. sdram interface timing symbol parameter registers rbitpacc programmable bank i access time 0x4010, 0x4014 rbitpa programmable bank i page address access time 0x4010, 0x4014 table 9. static memory timing parameters
micrel, inc. ks8695x june 2006 39 m9999-060106 package information 208-pin pqfp (pq) micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http:/www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in pers onal injury. life support devices or system s are devices or systems that (a) are in tended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significan t injury to the user. a purchaser?s use or sale of micrel produc ts for use in life support app liances, devices or systems is a purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2004 micrel, incorporated.

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